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How To Make a Photonic Integrated Circuit

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December 1, 2022

How To Make a Photonic Integrated Circuit

Photonics is one of the enabling technologies of the future. Light is the fastest information…

Photonics is one of the enabling technologies of the future. Light is the fastest information carrier in the universe and can transmit this information while dissipating less heat and energy than electrical signals. Thus, photonics can dramatically increase the speed, reach, and flexibility of communication networks and cope with the ever-growing demand for more data. And it will do so at a lower energy cost, decreasing the Internet’s carbon footprint. Meanwhile, fast and efficient photonic signals have massive potential for sensing and imaging applications in medical devices, automotive LIDAR, agricultural and food diagnostics, and more.

Given its importance, we want to explain how photonic integrated circuits (PICs), the devices that enable all these applications, are made.

Designing a PIC

The process of designing a PIC should translate an initial application concept into a functioning photonics chip that can be manufactured. In a short course at the OFC 2018 conference, Wim Bogaerts from Ghent University summarized the typical PIC design process in the steps we will describe below.

Figure 1 Summary of the steps in a PIC design flow process

Concept and Specifications: We first have to define what goes into the chip. A chip architect normally spends time with the customer to understand what the customer wants to achieve with the chip and all the conditions and situations where the chip will be used. After these conversations, the chip application concept becomes a concrete set of specifications that are passed on to the team that will design the internals of the chip. These specs will set the performance targets of the PIC design.
Design Function: Having defined the specs, the design team will develop a schematic circuit diagram that captures the function of the PIC. This diagram is separated into several functional blocks: some of them might already exist, and some of them might have to be built. These blocks include lasers, modulators, detectors, and other components that can manipulate light in one way or another.
Design Simulation: Making a chip costs a lot of money and time. With such risks, a fundamental element of chip design is to accurately predict the chip’s behavior after it is manufactured. The functional blocks are placed together, and their behavior is simulated using various physical models and simulation tools. The design team often uses a few different simulation approaches to reduce the risk of failure after manufacturing.
Design Layout: Now, the design team must translate the functional chip schematic into a proper design layout that can be manufactured. The layout consists of layers, component positions, and geometric shapes that represent the actual manufacturing steps. The team uses software that translates these functions into the geometric patterns to be manufactured, with human input required for the trickiest placement and geometry decisions.
Check Design Rules: Every chip fabrication facility will have its own set of manufacturing rules. In this step, the design team verifies that the layout agrees with these rules.
Verify Design Function: This is a final check to ensure that the layout actually performs as was originally intended in the original circuit schematic. The layout process usually leads to new component placement and parasitic effects that were not considered in the original circuit schematic. These tests might require the design team to revisit previous functional or layout schematic steps.

The Many Steps of Fabricating a PIC

Manufacturing semiconductor chips for photonics and electronics is one of the most complex procedures in the world. For example, back in his university days, EFFECT Photonics President Boudewijn Docter described a fabrication process with a total of 243 steps!

Yuqing Jiao, Associate Professor at the Eindhoven University of Technology (TU/e), explains the fabrication process in a few basic, simplified steps:

Grow or deposit your chip material
Print a pattern on the material
Etch the printed pattern into your material
Do some cleaning and extra surface preparation
Go back to step 1 and repeat as needed

Real life is, of course, a lot more complicated and will require cycling through these steps tens of times, leading to processes with more than 200 total steps. Let’s go through these basic steps in a bit more detail.

Figure 2 Basic steps of a semiconductor fabrication process that are repeated in a single fabrication cycle. An entire wafer manufacturing process requires tens of these cycles.

Layer Epitaxy and Deposition: Different chip elements require different semiconductor material layers. These layers can be grown on the semiconductor wafer via a process called epitaxy or deposited via other methods (which are summarized in this article).

Figure 3: Simplified example of PIC elements and the different material layers they require. Source: Smit et al. (2014)

Lithography (i.e. printing): There are a few lithography methods, but the one used for high-volume chip fabrication is projection optical lithography. The semiconductor wafer is coated with a photosensitive polymer film called a photoresist. Meanwhile, the design layout pattern is transferred to an opaque material called a mask. The optical lithography system projects the mask pattern onto the photoresist. The exposed photoresist is then developed (like photographic film) to complete the pattern printing.

Figure 4 Comparison of different optical lithography approaches. Contact and proximity printing keep the mask in contact with or close to the sample. Projection printing keeps the mask further away and is initially more expensive, but it is the technology of choice for high-volume manufacturing. Source: J. Shen, University of Waterloo PhD Thesis (2018)

Etching: Having “printed” the pattern on the photoresist, it is time to remove (or etch) parts of the semiconductor material to transfer the pattern from the resist into the wafer. There are several techniques that can be done to etch the material, which are summarized in this article.

Figure 5: Example of what a semiconductor wafer with resist (red color) on top of it looks like before and after an etching step.

Cleaning and Surface Preparation: After etching, a series of steps will clean and prepare the surface before the next cycle.
- Passivation: Adding layers of dielectric material (such a silica) to “passivate” the chip and make it more tolerant to environmental effects.
- Planarization: Making the surface flat in preparation of future lithography and etching steps.
- Metallization: Depositing metal components and films on the wafer. This might be done for future lithography and etching steps, or at the end to add electrical contacts to the chip.

Figure 6 summarizes how an InP photonic device looks after the steps of layer epitaxy, etching, dielectric deposition and planarization, and metallization.

Figure 6 Cross-section of a semiconductor wafer structure after: (a) epitaxial growth, (b) etching, (c) passivation and planarization, (d) metallization.

The Expensive Process of Testing and Packaging

Chip fabrication is a process with many sources of variability, and therefore much testing is required to make sure that the fabricated chip agrees with what was originally designed and simulated. Once that is certified and qualified, the process of packaging and assembling a device with the PIC follows.

While packaging, assembly, and testing are only a small part of the cost of electronic systems, the reverse happens with photonic systems. Researchers at the Technical University of Eindhoven (TU/e) estimate that for most Indium Phosphide (InP) photonics devices, the cost of packaging, assembly, and testing can reach around 80% of the total module cost. There are many research efforts in motion to reduce these costs, which you can learn more about in one of our previous articles.

Figure 7. Process cost breakdown of an InP PIC-based module as a percentage of the overall cost of manufacturing. Source: Latkowski et al., 2019

Especially after the first fabrication run of a new chip, there will be a few rounds of characterization, validation and revisions to make sure the chip performs up to spec. After this first round of characterization and validation, the chip must be made ready for mass production, which requires a series of reliability tests in several environmental different conditions. You can learn more about this process in our previous article on industrial hardening. For example, different applications need different certification of the temperatures in which the chip must operate in.

Temperature Standard	Temperature Range (°C)
Temperature Standard	Min	Max
Commercial (C-temp)	0	70
Extended (E-temp)	-20	85
Industrial (I-temp)	-40	85
Automotive / Full Military	-40	125

Table 1: Comparing the temperature ranges of different temperature hardening standards, including industrial and automotive/full military applications

Takeaways

The process of making photonic integrated circuits is incredibly long and complex, and the steps we described in this article are a mere simplification of the entire process. It requires tremendous amount of knowledge in chip design, fabrication, and testing from experts in different fields all around the world. EFFECT Photonics was founded by people who fabricated these chips themselves, understand the process intimately, and developed the connections and network to develop cutting-edge PICs at scale.

Tags: building blocks, c-temp, coherent, die testing, DSP, electron beam lithography, faults, I-temp, imprint lithography, InP, interfaces, optical lithography, reach, scale, wafer testing

What are FEC and PCS, and Why do They Matter

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November 16, 2022

What are FEC and PCS, and Why do They Matter?

Coherent transmission has become a fundamental component of optical networks to address situations where direct…

Coherent transmission has become a fundamental component of optical networks to address situations where direct detect technology cannot provide the required capacity and reach.

While Direct Detect transmission only uses the amplitude of the light signal, Coherent optical transmission manipulates three different light properties: amplitude, phase, and polarization. These additional degrees of modulation allow for faster optical signals without compromising the transmission distance. Furthermore, coherent technology enables capacity upgrades without replacing the expensive physical fiber infrastructure on the ground.

However, the demand for data never ceases, and with it, developers of digital signal processors (DSPs) have had to figure out ways to improve the efficiency of coherent transmission. In this article, we will briefly describe the impact of two algorithms that DSP developers use to make coherent transmission more efficient: Forward Error Correction (FEC) and Probabilistic Constellation Shaping (PCS).

What is Forward Error Correction?

Forward Error Correction (FEC) implemented by DSPs has become a vital component of coherent communication systems. FEC makes the coherent link much more tolerant to noise than a direct detect system and enables much longer reach and higher capacity. Thanks to FEC, coherent links can handle bit error rates that are literally a million times higher than a typical direct detect link.

Let’s provide a high-level overview of how FEC works. An FEC encoder adds a series of redundant bits (called overhead) to the transmitted data stream. The receiver can use this overhead to check for errors without asking the transmitter to resend the data.

Figure 1 Simplified diagram of a network link with Forward Error Correction (FEC).

In other words, FEC algorithms allow the DSP to enhance the link performance without changing the hardware. This enhancement is analogous to imaging cameras: image processing algorithms allow the lenses inside your phone camera to produce a higher-quality image.

We must highlight that FEC is a block of an electronic DSP engine with its own specialized circuitry and algorithms, so it is a separate piece of intellectual property. Therefore, developing the entire DSP electronic engine (see Figure 2 for the critical component blocks of a DSP) requires ownership or access to specific FEC intellectual property.

Figure 2 Layout of the electronic engine used in a coherent optical transceiver, including the sequence the signal follows when processed by the engine.

What is Probabilistic Constellation Shaping?

DSP developers can transmit more data by transmitting more states in their quadrature-amplitude modulation process. The simplest kind of QAM (4-QAM) uses four different states (usually called constellation points), combining two different intensity levels and two different phases of light.

By using more intensity levels and phases, more bits can be transmitted in one go. State-of-the-art commercially available 400ZR transceivers typically use 16-QAM, with sixteen different constellation points that arise from combining four different intensity levels and four phases. However, this increased transmission capacity comes at a price: a signal with more modulation orders is more susceptible to noise and distortions. That’s why these transceivers can transmit 400Gbps over 100km but not over 1000km.

One of the most remarkable recent advances in DSPs to increase the reach of light signals is Probabilistic Constellation Shaping (PCS). In the typical 16-QAM modulation used in coherent transceivers, each constellation point has the same probability of being used. This is inefficient since the outer constellation points that require more power have the same probability as the inner constellation points that require lower power.

Figure 3: Comparison of conventional 16-QAM and a 16-QAM that uses Probabilistic Constellation Shaping (PCS). Diagram inspired by a figure from Infinera.

PCS uses the low-power inner constellation points more frequently and the outer constellation points less frequently, as shown in Figure 3. This feature provides many benefits, including improved tolerance to distortions and easier system optimization to specific bit transmission requirements. If you want to know more about it, please read the explainers here and here.

The Importance of Standardization and Reconfigurability

Algorithms like FEC and PCS have usually been proprietary technologies. Equipment and component manufacturers closely guarded their algorithms because they provided a critical competitive advantage. However, this often meant that coherent transceivers from different vendors could not operate with each other, and a single vendor had to be used for the entire network deployment.

Over time, coherent transceivers have increasingly needed to become interoperable, leading to some standardization in these algorithms. For example, the 400ZR standard for data center interconnects uses a public algorithm called concatenated FEC (CFEC). In contrast, some 400ZR+ MSA standards use open FEC (oFEC), which provides a more extended reach at the cost of a bit more bandwidth and energy consumption. For the longest possible link lengths (500+ kilometers), proprietary FECs become necessary for 400G transmission. Still, at least the public FEC standards have achieved interoperability for a large segment of the 400G transceiver market. Perhaps in the future, this could happen with PCS methods.

Future DSPs could switch among different algorithms and methods to adapt to network performance and use cases. For example, let’s look at the case of upgrading a long metro link of 650km running at 100 Gbps with open FEC. The operator needs to increase that link capacity to 400 Gbps, but open FEC could struggle to provide the necessary link performance. However, if the DSP can be reconfigured to use a proprietary FEC standard, the transceiver will be able to handle this upgraded link. Similarly, longer reach could be achieved if the DSP activates its PCS feature.

	400 ZR	Open ZR+	Proprietary Long Haul
Target Application	Edge data center interconnect	Metro, Regional data center interconnect	Long-Haul Carrier
Target Reach @ 400G	120km	500km	1000 km
Form Factor	QSFP-DD/OSFP	QSFP-DD/OSFP	QSFP-DD/OSFP
FEC	CFEC	oFEC	Proprietary
Standards / MSA	OIF	OpenZR+ MSA	Proprietary

Table 1: Summary of different use cases and standards for a 400G pluggable transceiver.

Takeaways

The entire field of communication technology can arguably be summarized with a single question: how can we transmit more information into a single frequency-limited signal over the longest possible distance?

DSP developers have many tools to answer this question, and two of them are FEC and PCS. Both technologies make coherent links much more tolerant of noise and can extend their reach. Future pluggables that handle different use cases must use different coding, error coding, and modulation schemes to adapt to different network requirements.

There are still many challenges ahead to improve DSPs and make them transmit even more bits in more energy-efficient ways. Now that EFFECT Photonics has incorporated talent and intellectual property from Viasat’s Coherent DSP team, we hope to contribute to this ongoing research and development and make transceivers faster and more sustainable than ever.

Tags: coherent, constellation shaping, DSP, DSPs, error compensation, FEC, PCS, power, Proprietary, reach, reconfigurable, standardized, standards

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